AT32AP7002_1 Datasheet, PDF (606/896 Pages) ATMEL Corporation – AVR32 32-bit Microcontroller

AT32AP7002
31.6.5 DMA
USB packets of any length may be transferred when required by the USBA Device. These trans-
fers always feature sequential addressing.
Packet data HSB bursts may be locked on a DMA buffer basis for drastic overall HSB bus band-
width performance boost with paged memories. These clock-cycle consuming memory row (or
bank) changes will then likely not occur, or occur only once instead of dozens times, during a
single big USB packet DMA transfer in case another HSB master addresses the memory. This
means up to 128-word single-cycle unbroken HSB bursts for Bulk endpoints and 256-word sin-
gle-cycle unbroken bursts for isochronous endpoints. This maximum burst length is then
controlled by the lowest programmed USB endpoint size (EPT_SIZE bit in the EPTCFGx regis-
ter) and DMA Size (BUFF_LENGTH bit in the DMACONTROLx register).
The USBA device average throughput may be up to nearly 60 MBytes. Its internal slave average
access latency decreases as burst length increases due to the 0 wait-state side effect of
unchanged endpoints. If at least 0 wait-state word burst capability is also provided by the exter-
nal DMA HSB bus slaves, each of both DMA HSB busses need less than 50% bandwidth
allocation for full USBA bandwidth usage at 30 MHz, and less than 25% at 60 MHz.
The USBA DMA Channel Transfer Descriptor is described in ”USBA DMA Channel Transfer
Descriptor” on page 665
Figure 31-5. Example of DMA Chained List:
UDPHS Registers
(Current Transfer Descriptor)
UDPHS Next Descriptor
DMA Channel Address
Transfer Descriptor
Next Descriptor Address
DMA Channel Address
DMA Channel Control
Transfer Descriptor
Next Descriptor Address
DMA Channel Address
Transfer Descriptor
DMA Channel Control
DMA Channel Control
Next Descriptor Address
DMA Channel Address
DMA Channel Control
Null
Memory Area
Data Buff 1
Data Buff 2
Data Buff 3
31.6.6 Handling Transactions with USB V2.0 Device Peripheral
31.6.6.1 Setup Transaction
The setup packet is valid in the DPR while RX_SETUP is set. Once RX_SETUP is cleared by
the application, the USBA accepts the next packets sent over the device endpoint.
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