SAM9M11_14 Datasheet, PDF (73/1488 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

The Reset Controller can also be programmed to generate an interrupt instead of generating a reset. To do so, the
bit URSTIEN in RSTC_MR must be written at 1.
11.4.2.2 NRST External Reset Control
The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out”
signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion
duration, named EXTERNAL_RESET_LENGTH, lasts 2^(ERSTL+1) Slow Clock cycles. This gives the approximate
duration of an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the
NRST pulse.
This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is
driven low for a time compliant with potential external devices connected on the system reset.
As the field is within RSTC_MR, which is backed-up, this field can be used to shape the system power-up reset for
devices requiring a longer startup time than the Slow Clock Oscillator.
11.4.3 BMS Sampling
The product matrix manages a boot memory that depends on the level on the BMS pin at reset. The BMS signal is
sampled three slow clock cycles after the Core Power-On-Reset output rising edge.
Figure 11-3. BMS Sampling
SLCK
Core Supply
POR output
BMS Signal
proc_nreset
XXX
BMS sampling delay
= 3 cycles
H or L
11.4.4 Reset States
The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports
the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is
performed when the processor reset is released.
11.4.4.1 General Reset
A general reset occurs when VDDBU and VDDCORE are powered on. The backup supply POR cell output rises
and is filtered with a Star tup Counter, which operates at Slow Clock. The purpose of this counter is to make sure
the Slow Clock oscillator is stable before starting up the device. The length of startup time is hardcoded to comply
with the Slow Clock Oscillator startup time.
After this time, the processor clock is released at Slow Clock and all the other signals remain valid for 3 cycles for
proper processor and logic reset. Then, all the reset signals are released and the field RSTTYP in RSTC_SR
reports a General Reset. As the RSTC_MR is reset, the NRST line rise s 2 cycles after the backup_nreset, as
ERSTL defaults at value 0x0.
SAM9M11 [DATASHEET]
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Atmel-6437F-ATARM-SAM9M11-Datasheet_21-Oct-14