SAM9M11_14 Datasheet, PDF (1378/1488 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

In monochrome mode, Horizontal_display_size is equal to the number of horizontal pixels. The number_data_lines
is equal to the number of bits of the interface in single scan mode; number_data_lines is equal to half the bits of
the interface in dual scan mode.
In color mode, Horizontal_display_size equals three times the number of horizontal pixels.
In TFT Mode:
HOZVAL = Horizontal_display_size – 1
LINEVAL = Vertical_display_size – 1
The frame rate equation is used first without considering the clock periods added at the end beginning or at the
end of each line to determine, approximately, the LCDDOTCK rate:
f_{lcd_pclk} = (HOZVAL + 5) × (f_{lcd_vsync} × (LINEVAL + 1))
With this value, the CLKVAL is fixed, as well as the corresponding LCDDOTCK rate.
Then select VHDLY, HPW and HBP according to the type of LCD used and “Equation 1” on page 1375.
Finally, the frame rate is adjusted to 70 Hz - 75 Hz with the HFP value:
HFP = f_LCDDOTCK ×
------------------------------------------------------1-------------------------------------------------------
f_LCDVSYNC × (LINEVAL + VBP + VFP + 1)
– (VHDLY + HPW + HPB + HOZVAL + 4)
The line counting is controlled by the read-only field LINECNT of LC DCON1 register. The LINECNT field
decreases by one unit at each falling edge of LCDHSYNC.
48.6.2.10Display
This block is used to c onfigure the polarity of the data and control signals. The polarity of all clock signals can be
configured by LCDCON2[12:8] register setting.
This block also generates the lcd_pwr signal internally used to control the state of the LCD pins and to turn on and
off by software the LCD module.
It is also available on the LCDPWR pin.
This signal is controlled by the PWRCO N register and respects the number of frames configured in the
GUARD_TIME field of PWRCON register (PWRCON[7:1]) between the write access to L CD_PWR field
(PWRCON[0]) and the activation/deactivation of lcd_pwr signal.
The minimum value for the GUARD_TIME field is one frame. This gives the DMA Controller enough time to fill the
FIFOs before the start of data transfer to the LCD.
48.6.2.11PWM
This block generates the LCD contrast control signal (LCDCC) to make possible the control of the display's
contrast by software. This is an 8-bit PWM (Pulse Width Modulation) signal that can be converted to an analog
voltage with a simple passive filter.
The PWM module has a free-r unning counter whose value is compared against a compare register
(CONSTRAST_VAL register). If the value in the counter is less than that in the register, the output brings the value
of the polarity (POL) bit in the PWM control register: CONTRAST_CTR. Otherwise, the opposite value is output.
Thus, a periodic waveform with a pulse width proportional to the value in the compare register is generated.
Due to the comparison mechanism, the output pulse has a width between zero and 255 PWM counter cycles.
Thus by adding a simple passive filter outside the chip, an analog voltage between 0 and (255/256) × VDD can be
obtained (for the positive polarity case, or between (1/256) × VDD and VDD for the negative polarity case). Other
voltage values can be obtained by adding active external circuitry.
1378
SAM9M11 [DATASHEET]
Atmel-6437F-ATARM-SAM9M11-Datasheet_21-Oct-14