SAM9M11_14 Datasheet, PDF (688/1488 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

 Configuration of the clock generator if DIVA and DIVB are required
 Selection of the clock for each channel (CPRE field in the PWM_CMRx register)
 Configuration of the waveform alignment for each channel (CALG field in the PWM_CMRx register)
 Configuration of the period for each channel (CPRD in the PWM_CPRDx register). Writing in PWM_CPRDx
Register is possible while the channel is disabled. After validation of the channel, the user must use
PWM_CUPDx Register to update PWM_CPRDx as explained below.
 Configuration of the duty cycle for each channel (CDTY in the PWM_CDTYx register). Writing in
PWM_CDTYx Register is possible while the channel is disabled. After validation of the channel, the user
must use PWM_CUPDx Register to update PWM_CDTYx as explained below.
 Configuration of the output waveform polarity for each channel (CPOL in the PWM_CMRx register)
 Enable Interrupts (Writing CHIDx in the PWM_IER register)
 Enable the PWM channel (Writing CHIDx in the PWM_ENA register)
It is possible to synchron ize different channels by enabling them at the same time by means of writing
simultaneously several CHIDx bits in the PWM_ENA register.
 In such a situation, all channels may have the same clock selector configuration and the same period
specified.
33.6.3.2 Source Clock Selection Criteria
The large number of sou rce clocks can make selection difficult. The relationship between the value in the Period
Register (PWM_CPRDx) and the Duty Cy cle Register (PWM_CDTYx) can help the user in choosing. The event
number written in the Period Register gives the PWM accuracy. The Duty Cycle quantum cannot be lowe r than
1/PWM_CPRDx value. The higher the value of PWM_CPRDx, the greater the PWM accuracy.
For example, if the user sets 15 (in decimal) in PWM_CPRDx, the user is able to set a value between 1 up to 14 in
PWM_CDTYx Register. The resulting duty cycle quantum cannot be lower than 1/15 of the PWM period.
33.6.3.3 Changing the Duty Cycle or the Period
It is possible to modulate the output waveform duty cycle or period.
To prevent unexpected output waveform, the user must use the update register (PWM_CUPDx) to change
waveform parameters while the channel is still enabled. The user can write a new period value or duty cycle value
in the update register (PWM_CUPDx). This register holds the new value until the end of the current cycle and
updates the value for the next cycle. Depending on the CPD field in the PWM_CMRx register, PWM_CUPDx either
updates PWM_CPRDx or PWM_CDTYx. Note that even if the update register is used, the period must not be
smaller than the duty cycle.
688
SAM9M11 [DATASHEET]
Atmel-6437F-ATARM-SAM9M11-Datasheet_21-Oct-14