SAM9M11_14 Datasheet, PDF (336/1488 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

from the OSCOUNT value. Since the OSCOUNT value is coded with 8 bits, the maximum startup time is about 62
ms.
When the counter reaches 0, the MOSCS bit is set, indicating that the main clock is valid. Setting the MOSCS bit in
PMC_IMR can trigger an interrupt to the processor.
24.6.4 Main Oscillator Bypass
The user can input a clock on the device instead of connecting a crystal. In this case, the user has to provide the
external clock signal on the XIN pin. The input characteristics of the XIN pin under these conditions are given in the
product electrical characteristics section. The programmer has to be sure to set the OSCBYPASS bit to 1 and the
MOSCEN bit to 0 in the Main OSC register (CKGR_MOR) for the external clock to operate properly.
24.7
Divider and PLLA Block
The PLLA embeds an input divider to increase the accuracy of the resulting clock signals. However, the user must
respect the PLLA minimum input frequency when programming the divider.
The PLLA embeds also an output divisor by 2.
Figure 24-6 shows the block diagram of the divider and PLLA block.
Figure 24-6. Divider and PLLA Block Diagram
DIVA
MULA OUTA
PLLADIV2
MAINCK
Divider
PLLA
/1 or /2
Divider
PLLACK
SLCK
PLLACOUNT
PLLA
Counter
LOCKA
24.7.1 Divider and Phase Lock Loop Programming
The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the output of the
corresponding divider and the PLL output is a continuous signal at level 0. On reset, each DIV field is set to 0, thus
the corresponding PLL input clock is set to 0.
The PLLA allows multiplication of the divider’s outputs. The PLLA clock signal has a frequency that depends on
the respective source signal frequency and on the paramet ers DIVA and MULA. The factor applied to the source
signal frequency is (MULA + 1)/DIVA. When MULA is written to 0, the PLLA is disabled and its power consumption
is saved. Re-enabling the PLLA can be performed by writing a value higher than 0 in the MUL field.
Whenever the PLLA is re-enabled or one of its parameters is changed, the LOCKA bit in PMC_SR is automatically
cleared. The values written in the PLLACOUNT field in CKGR_PLLAR are loaded in the PLLA counter. The PLLA
counter then decrements at the speed of the Slow Clock until it reaches 0. At this time, the LOCK bit is set in
PMC_SR and can trigger an interrupt to the processor. The user has to load the number of Slo w Clock cycles
required to cover the PLLA transient time into the PLLACOUNT field.
The PLLA clock can be divided by 2 by writing the PLLADIV2 bit in PMC_MCKR register.
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SAM9M11 [DATASHEET]
Atmel-6437F-ATARM-SAM9M11-Datasheet_21-Oct-14