SAM9M11_14 Datasheet, PDF (472/1488 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

Table 29-2. I/O Lines
SPI0
SPI0
SPI0
SPI0
SPI0
SPI0
SPI0
SPI1
SPI1
SPI1
SPI1
SPI1
SPI1
SPI1
SPI0_NPCS0
SPI0_NPCS1
SPI0_NPCS1
SPI0_NPCS2
SPI0_NPCS2
SPI0_NPCS3
SPI0_SPCK
SPI1_MISO
SPI1_MOSI
SPI1_NPCS0
SPI1_NPCS1
SPI1_NPCS2
SPI1_NPCS3
SPI1_SPCK
PB3
A
PB18
B
PD24
A
PB19
B
PD25
A
PD27
B
PB2
A
PB14
A
PB15
A
PB17
A
PD28
B
PD18
A
PD19
A
PB16
A
29.6.2 Power Management
The SPI may be clocked through the Power Management Controller (PMC), thus the programmer must first
configure the PMC to enable the SPI clock.
29.6.3 Interrupt
The SPI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC).Handling the SPI
interrupt requires programming the AIC before configuring the SPI.
Table 29-3. Peripheral IDs
Instance
ID
SPI0
14
SPI1
15
29.6.4 Peripheral DMA Controller (PDMA) Direct Memory Access Controller (DMAC)
The SPI interface can be used in conjunction with the PDMA DMAC in order to reduce processor overhead. For a
full description of the PDMA DMAC, refer to the corresponding section in the full datasheet.
29.7 Functional Description
29.7.1 Modes of Operation
The SPI operates in Master Mode or in Slave Mode.
Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register. The pins NPCS0 to
NPCS3 are all configured as outputs, the SPCK pin is driven, the MISO line is wired on the receiver input and the
MOSI line driven as an output by the transmitter.
If the MSTR bit is written at 0, the SPI operates in Slave Mode. The MISO line is driven by the transmitter output,
the MOSI line is wired on the receiver input, the SPCK pin is driven by the transmitter to synchronize the receiver.
472
SAM9M11 [DATASHEET]
Atmel-6437F-ATARM-SAM9M11-Datasheet_21-Oct-14