AT91SAM7A2_04 Datasheet, PDF (65/369 Pages) ATMEL Corporation – AT91 ARM Thumb-based Microcontrollers

Configuration
Interrupt Handling
AT91SAM7A2
If the interrupt is not considered due to a bug, a reset occurs when the watchdog
counter reaches 0.
• Configuration of WD_MR: Choice of the clock to decrement counter, preload value
from which the counter starts to decrement.
• Configuration of WD_ PWR: Upper limit of the window from which it generates an
interrupt when reached and the bit which restarts the counter only within this
window.
• Configuration of WD_IER: Enable Interrupt at the peripheral level when the window
is reached (WDPEND bit) or when the counter overflow (WDOVF bit if watchdog
reset is not enabled), GIC must be configured.
• Configuration of WD_OMR: Enable the watchdog (start decrementing the counter)
and enable the watchdog reset in case of counter overflow.
• IRQ Entry and call C function.
• Read WD_SR and verify the source of the interrupt.
• Clear the corresponding interrupt at peripheral level by writing in the WD_CSR.
• Interrupt treatment. If this is a pending window interrupt, restart the watchdog by
writing in WD_CR.
• IRQ Exit.
6021A–ATARM–07/04
PRELIMINARY
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