AT91SAM7A2_04 Datasheet, PDF (109/369 Pages) ATMEL Corporation – AT91 ARM Thumb-based Microcontrollers

AT91SAM7A2
Figure 47. Signal Description
adc_clk
start
hold
0 1 23 4 56 7 89
D[9:0]
eoc
0
1 2 3 4 567 89
Data Valid
0
12
3
When start is high, the cell is reset and the internal clock is inhibited. The D[9:0] signal is
at 512, so the internal ADC output is at (VREFP - GND)/2. The hold output is low, so the
input voltage at the Sample and Hold stage of the comparator is sampled.
When the start goes low, the hold signal goes high with the next falling clock edge, and
the input voltage is stored on the Sample and Hold capacitor. The comparator performs
a comparison between the stored input voltage and the ADC output.
With the next rising clock signal, the comparator output becomes valid, this value being
stored as D[9] in the internal register. The internal shift register now sets D[8] high, and
a new comparison is performed. The next rising edge of clock stores the result in D[8].
After another 8 low-pulse of clock, all 10 bits are valid at output D[9:0]. The End of Con-
version signal (EOC) is set high. The input is sampled again as the hold signal goes low
and a new conversion can be started with a high-pulse of the start signal.
6021A–ATARM–07/04
PRELIMINARY
109