AT91SAM7A2_04 Datasheet, PDF (125/369 Pages) ATMEL Corporation – AT91 ARM Thumb-based Microcontrollers

AT91SAM7A2
Universal Synchronous/ Asynchronous Receiver/Transmitter (USART)
Overview
Block Diagram
The AT91SAM7A2 includes two USARTs. Each transmitter and receiver module is con-
nected to the Peripheral Data Controller.
The main features are:
• Programmable baud rate generator
• Parity, framing and overrun error detection
• Supports Hardware LIN protocol (specification 1.2)
• Idle flag for J1587 protocol
• Line break generation and detection
• Automatic echo, local loopback and remote loopback channel modes
• Multi-drop mode: address detection and generation
• Interrupt generation
• Two dedicated Peripheral Data Controller channels per USART
• 5 to 9-bit character length
Figure 49. USART Block Diagram
ASB
AMBA
Peripheral Data
Controller
Channel Channel
TX
RX
APB
TX_RDY END
RX_RDY
Control Logic
USART Channel
Receiver
RXD
INT
Interrupt Control
PIO
CORECLK
USART
CLOCK
PMC
Baud Rate
Generator
Transmitter
Baud Rate
Clock
PIO CLOCK
TXD
SCK
Baud Rate Generator
The baud rate generator provides the bit period clock, named the baud rate clock, to
both the receiver and the transmitter.
The baud rate generator can select between external and internal clock sources. The
external clock source is SCK. The internal clock sources can be either CORECLK or
CORECLK divided by 8 (CORECLK/8).
6021A–ATARM–07/04
PRELIMINARY
125