AT91SAM7A2_04 Datasheet, PDF (111/369 Pages) ATMEL Corporation – AT91 ARM Thumb-based Microcontrollers

Modes of Operation
6021A–ATARM–07/04
AT91SAM7A2
A single conversion at the maximum clock rate permitted (i.e. 700 kHz) will occur in 15.7
ms.
The ADC starts the conversion by writing 1 in the START bit of the control register
(ADC_CR).
Writing 1 to the START bit starts the conversion even if the analog structure begins the
conversion when start goes low, the interface transmits the opposite of the start com-
mand to the analog part.
For a conversion, different input combinations can be selected. The 3-bit NBRCH[2:0]
indicates how many inputs will be converted (the real number is the value of NBRCH
incremented by one).
The result of the conversion is stored in the convert data register (ADC_DR). When the
conversion is complete, the analog part activates the EOC bit in the ADC Status register
(ADC_SR) and sends an EOC signal to the PDC which can take the result and write at a
memory location. The EOC bit in ADC_SR (Status Register) is cleared when the
ADC_DR (Convert Data Register) is read. If a new result arrives before the PDC or the
CPU read the old data, the Overrun bit (OVR) is set active to specify to the microproces-
sor that data is lost. If the PDC is used to save the results and if the transfer of all the
data is finished, the PDC sets the TEND bit to a logical 1.
The READY bit is set after an absolute time of 4 µs after an enable command, which
corresponds to the initialization time of the analog part. This time is necessary to stabi-
lize the analog structure and does not depend on the choice of the ADC clock or the
names of analog inputs considered. The number of master clock periods necessary to
wait during 4 µs is remembered in the STARTUPTIME bits of the mode register.
The user can make conversions in continuous mode. This status is indicated by the
CONTCV bit of the ADC Mode Register (ADC_MR). In this case, the microprocessor
gives the first start to the ADC and the peripheral does not stop the conversion until the
STOP bit of the ADC Control Register is set, or when the TEND bit of the status register
is set if STOPEN is active. However, the user should be vigilant, because after a stop
command in continuous mode, the ADC finishes the ongoing conversion and this may
appear to be an extra conversion. The digital interface between the analog part and the
APB bus is in stand alone mode; this permits conversion without any help. This mode
can be associated with multiple inputs as well as a single input. The different steps of
the conversion are equivalent to those of a single conversion.
If the ADC is configured in continuous mode, a particular sequence should be observed
at the end of a PDC transfer. When a set of PDC transfers have reached the end, the
ADC runs an extra conversion. The CPU must clear the TEND flag before the end (EOC
in ADC_SR) of the extra conversion. If the software can not ensure clearing the TEND
flag before the EOC of the extra conversion, two solutions are available:
• When a set of PDC transfers is completed, before starting an additional set of ADC
conversions associated with PDC transfers, software must reset the ADC (SWRST
in ADC_CR).
• When a set of PDC transfers is completed, before starting an additional set of ADC
conversions associated with PDC transfers, software should start a conversion, wait
for the EOC flag in the ADC_SR register and read ADC_DR to clear the EOC flag.
The ADC can be active or shutdown; in the latter case it is in a power saving mode.
At any time the software can program the ADC to be disabled to save power. Setting the
ADCDIS bit of the ADC Control register will put the ADC Analog circuitry into standby
mode. To reduce the power consumption near to 0, the user can switch off the ADC
PRELIMINARY
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