SAM7S161_14 Datasheet, PDF (64/775 Pages) ATMEL Corporation – ARM-based Flash MCU

• If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted,
depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in
a User Reset state.
• If WDRPROC = 1, only the processor reset is asserted.
The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if
WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset, and the Watchdog is enabled by
default and with a period set to a maximum.
When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller.
Figure 13-8. Watchdog Reset
SLCK
MCK
Any
Freq.
wd_fault
proc_nreset
RSTTYP
Any
periph_nreset
Only if
WDRPROC = 0
NRST
(nrst_out)
Processor Startup
= 3 cycles
XXX
0x2 = Watchdog Reset
EXTERNAL RESET LENGTH
8 cycles (ERSTL=2)
SAM7S Series [DATASHEET] 64
6175M–ATARM–26-Oct-12