SAM7S161_14 Datasheet, PDF (299/775 Pages) ATMEL Corporation – ARM-based Flash MCU

Figure 29-7. Master Write with One Byte Internal Address and Multiple Data Bytes
TWD S
DADR
W A IADR(7:0) A
DATA n
A
DATA n+5 A DATA n+x A P
TXCOMP
TXRDY
Write THR (Data n)
Write THR (Data n+1) Write THR (Data n+x) STOP sent automaticaly
Last data sent (ACK received and TXRDY = 1)
29.6.4
Master Receiver Mode
The read sequence begins by setting the START bit. After the start condition has been sent, the
master sends a 7-bit slave address to notify the slave device. The bit following the slave address
indicates the transfer direction, 1 in this case (MREAD = 1 in TWI_MMR). During the acknowl-
edge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull
it down in order to generate the acknowledge. The master polls the data line during this clock
pulse and sets the NACK bit in the status register if the slave does not acknowledge the byte.
If an acknowledge is received, the master is then ready to receive data from the slave. After data
has been received, the master sends an acknowledge condition to notify the slave that the data
has been received except for the last data, after the stop condition. See Figure 29-9. When the
RXRDY bit is set in the status register, a character has been received in the receive-holding reg-
ister (TWI_RHR). The RXRDY bit is reset when reading the TWI_RHR.
When a single data byte read is performed, with or without internal address (IADR), the START
and STOP bits must be set at the same time. See Figure 29-8. When a multiple data byte read is
performed, with or without internal address (IADR), the STOP bit must be set after the next-to-
last data received. See Figure 29-9. For Internal Address usage see Section 29.6.5.
Figure 29-8. Master Read with One Data Byte
TWD
S
DADR
RA
DATA
NP
TXCOMP
RXRDY
Write START &
STOP Bit
Read RHR
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
299