SAM7S161_14 Datasheet, PDF (370/775 Pages) ATMEL Corporation – ARM-based Flash MCU

Figure 31-9. Transmitter Status
Baud Rate
Clock
TXD
Write
US_THR
Start
Bit
D0
D1
D2
D3
D4
D5
D6
D7
ParityStop Start
Bit Bit Bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity Stop
Bit Bit
TXRDY
TXEMPTY
31.6.3.2 Asynchronous Receiver
If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver oversamples the RXD
input line. The oversampling is either 16 or 8 times the Baud Rate clock, depending on the OVER bit in the Mode
Register (US_MR).
The receiver samples the RXD line. If the line is sampled during one half of a bit time at 0, a start bit is detected
and data, parity and stop bits are successively sampled on the bit rate clock.
If the oversampling is 16, (OVER at 0), a start is detected at the eighth sample at 0. Then, data bits, parity bit and
stop bit are sampled on each 16 sampling clock cycle. If the oversampling is 8 (OVER at 1), a start bit is detected
at the fourth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle.
The number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter,
i.e. respectively CHRL, MODE9, MSBF and PAR. For the synchronization mechanism only, the number of stop
bits has no effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that resyn-
chronization between the receiver and the transmitter can occur. Moreover, as soon as the stop bit is sampled, the
receiver starts looking for a new start bit so that resynchronization can also be accomplished when the transmitter
is operating with one stop bit.
Figure 31-10 and Figure 31-11 illustrate start detection and character reception when USART operates in asyn-
chronous mode.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
370