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SAM7S161_14 Datasheet, PDF (600/775 Pages) ATMEL Corporation – ARM-based Flash MCU | |||
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⢠GOVRE inactive,
⢠previous data stored in LCDR being neither data from channel âyâ, nor data from channel âxâ.
GOVRE should be set but is not.
Problem Fix/Workaround
None
40.4.1.7 ADC: GOVRE Bit is not Set when Disabling a Channel
When disabling channel âyâ at the same instant as an end of conversion on channel âxâ, EOC[x] and DRDY being
already active, GOVRE does not rise.
Note: OVRE[x] rises as expected.
Problem Fix/Workaround
None
40.4.1.8 ADC: OVRE Flag Behavior
When the OVRE flag (on channel i) has been set but the related EOC status (of channel i) has been cleared (by a
read of CDRi or LCDR), reading the Status register at the same instant as an end of conversion (causing the set of
EOC status on channel i), does not lead to a reset of the OVRE flag (on channel i) as expected.
Problem Fix/Workaround:
None
40.4.1.9 ADC: EOC Set although Channel Disabled
If a channel is disabled while a conversion is running and if a read of CDR is performed at the same time as an end
of conversion of any channel occurs, the EOC of the channel with the conversion running may rise (whereas it has
been disabled).
Problem Fix/Workaround
Do not take into account the EOC of a disabled channel
40.4.1.10 ADC: Spurious Clear of EOC Flag
If âxâ and âyâ are two successively converted channels and âzâ is yet another enabled channel (âzâ being neither âxâ
nor âyâ), reading CDR on channel âzâ at the same instant as an end of conversion on channel âyâ automatically
clears EOC[x] instead of EOC[z].
Problem Fix/Workaround
None.
40.4.1.11 ADC: Sleep Mode
If Sleep mode is activated while there is no activity (no conversion is being performed), it will take effect only after
a conversion occurs.
Problem Fix/Workaround
To activate sleep mode as soon as possible, it is recommended to write successively, ADC Mode Register
(SLEEP) then ADC Control Register (START bit field); to start an analog-to-digital conversion, in order put ADC
into sleep mode at the end of this conversion.
40.4.2 Embedded Flash Controller (EFC)
40.4.2.1 EFC: Embedded Flash Access Time 1
The embedded Flash maximum access time is 20 MHz (instead of 30 MHz) at zero Wait State (FWS = 0).
SAM7S Series [DATASHEET]
6175MâATARMâ26-Oct-12
600
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