ATA6616C_14 Datasheet, PDF (60/274 Pages) ATMEL Corporation – 8K/16K Flash Microcontroller with LIN Transceiver, 5V Regulator and Watchdog

Table 4-14. Clock Prescaler Select
CLKPS3
CLKPS2
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
CLKPS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
CLKPS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Clock Division Factor
1
2
4
8
16
32
64
128
256
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
4.5.5.3 CLKCSR – Clock Control and Status Register
Bit
7
6
CLKCCE
–
Read/Write R/W
R
Initial Value
0
0
5
4
3
2
1
0
–
CLKRDY CLKC3 CLKC2 CLKC1 CLKC0 CLKCSR
R
R
R/W
R/W
R/W
R/W
0
0
0
0
0
0
• Bit 7 – CLKCCE: Clock Control Change Enable
The CLKCCE bit must be written to logic one to enable change of the CLKCSR bits. The CLKCCE bit is only updated when
the other bits in CLKCSR are simultaneously written to zero. CLKCCE is cleared by hardware four cycles after it is written or
when the CLKCSR bits are written. Rewriting the CLKCCE bit within this time-out period does neither extend the time-out
period, nor clear the CLKCCE bit.
• Bits 6:5 – Res: Reserved Bits
These bits are reserved bits in the Atmel^® ATtiny87/167 and will always read as zero.
• Bits 4 – CLKRDY: Clock Ready Flag
This flag is the output of the ‘Clock Availability’ logic.
This flag is cleared by the ‘Request for Clock Availability’ command or ‘Enable Clock Source’ command being entered.
It is set when ‘Clock Availability’ logic confirms that the (selected) clock is running and is stable. The delay from the request
and the flag setting is not fixed, it depends on the clock start-up time, the clock frequency and, of course, if the clock is alive.
The user’s code has to differentiate between ‘no_clock_signal’ and ‘clock_signal_not_yet_available’ condition.
• Bits 3:0 – CLKC3:0: Clock Control Bits 3 - 0
These bits define the command to provide to the ‘Clock Switch’ module. The special write procedure must be followed to
change the CLKC3..0 bits (See ”Bit 7 – CLKCCE: Clock Control Change Enable” on page 60.).
1. Write the Clock Control Change Enable (CLKCCE) bit to one and all other bits in CLKCSR to zero.
2. Within 4 cycles, write the desired value to CLKCSR register while clearing CLKCCE bit.
Interrupts should be disabled when setting CLKCSR register in order not to disturb the procedure.
60 ATA6616C/ATA6617C [DATASHEET]
9132I–AUTO–06/14