ATA6616C_14 Datasheet, PDF (115/274 Pages) ATMEL Corporation – 8K/16K Flash Microcontroller with LIN Transceiver, 5V Regulator and Watchdog

4.11.11.2 Timer/Counter0 Control Register B – TCCR0B
Bit
7
6
5
4
3
FOC0A
–
–
–
–
Read/Write
W
R
R
R
R
Initial Value
0
0
0
0
0
2
CS02
R/W
0
1
CS01
R/W
0
0
CS00
R/W
0
TCCR0B
• Bit 7 – FOC0A: Force Output Compare A
The FOC0A bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating
in PWM mode. When writing a logical one to the FOC0A bit, an immediate compare match is forced on the Waveform
Generation unit. The OC0A output is changed according to its COM0A1:0 bits setting. Note that the FOC0A bit is
implemented as a strobe. Therefore it is the value present in the COM0A1:0 bits that determines the effect of the forced
compare.
A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0A as TOP.
The FOC0A bit is always read as zero.
• Bit 6:3 – Res: Reserved Bits
These bits are reserved in the Atmel^® ATtiny87/167 and will always read as zero.
• Bit 2:0 – CS02:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table 4-34.
Table 4-34. Clock Select Bit Description
CS02
CS01
CS00
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Description
No clock source (Timer/Counter stopped).
clk_T0S (No prescaling)
clk_T0S/8 (from prescaler)
clk_T0S/32 (from prescaler)
clk_T0S/64 (from prescaler)
clk_T0S/128 (from prescaler)
clk_T0S/256 (from prescaler)
clk_T0S/1024 (from prescaler)
4.11.11.3 Timer/Counter0 Register – TCNT0
Bit
Read/Write
Initial Value
7
TCNT07
R/W
0
6
TCNT06
R/W
0
5
TCNT05
R/W
0
4
TCNT04
R/W
0
3
TCNT03
R/W
0
2
TCNT02
R/W
0
1
TCNT01
R/W
0
0
TCNT00
R/W
0
TCNT0
The Timer/Counter register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter.
Writing to the TCNT0 register blocks (removes) the compare match on the following timer clock. Modifying the counter
(TCNT0) while the counter is running, introduces a risk of missing a compare match between TCNT0 and the OCR0x
register.
ATA6616C/ATA6617C [DATASHEET] 115
9132I–AUTO–06/14