ATA6616C_14 Datasheet, PDF (163/274 Pages) ATMEL Corporation – 8K/16K Flash Microcontroller with LIN Transceiver, 5V Regulator and Watchdog

4.15.5.4 USICR – USI Control Register
Bit
Read/Write
Initial Value
7
USISIE
R/W
0
6
USIOIE
R/W
0
5
USIWM1
R/W
0
4
USIWM0
R/W
0
3
USICS1
R/W
0
2
USICS0
R/W
0
1
USICLK
W
0
0
USITC
W
0
USICR
The control register includes interrupt enable control, wire mode setting, clock select setting, and clock strobe.
• Bit 7 – USISIE: Start Condition Interrupt Enable
Setting this bit to one enables the start condition detector interrupt. If there is a pending interrupt when the USISIE and the
global interrupt enable flag is set to one, this will immediately be executed. Refer to the USISIF bit description for further
details.
• Bit 6 – USIOIE: Counter Overflow Interrupt Enable
Setting this bit to one enables the counter overflow interrupt. If there is a pending interrupt when the USIOIE and the global
interrupt enable flag is set to one, this will immediately be executed. Refer to the USIOIF bit description on page 162 for
further details.
• Bit 5:4 – USIWM1:0: Wire Mode
These bits set the type of wire mode to be used. Basically only the function of the outputs are affected by these bits. Data
and clock inputs are not affected by the mode selected and will always have the same function. The counter and USI data
register can therefore be clocked externally, and data input sampled, even when outputs are disabled. The relations
between USIWM1:0 and the USI operation is summarized in Table 4-45 on page 164.
ATA6616C/ATA6617C [DATASHEET] 163
9132I–AUTO–06/14