UG01 Datasheet, PDF (6/7 Pages) ATMEL Corporation – 0.6um ULC Series

UG Series
Power Consumption
Static Power Consumption for UG Series ULCs
There are three main factors to consider:
– Leakage in the core:
– P_LC = V_DD * I_CCSB * number of used gates
– Leakage in inputs and tri-stated outputs:
– P_LIO = V_DD * (I_IX * N + I_OZ * M)
– where: N = number of inputs
– M = number of tri-stated outputs
– Care must be taken to include the appropriate
figure for pins with pull-ups or pull-downs. In
practice, the static consumption calculation is
typically done to determine the standby current
of a device; in this case only those pins sourcing
current should be included, i.e. where V_IN or
V_OUT = V_DD.
– Dc power dissipation in driving I/O buffers due to
resistive loads:
– In practice, the static consumption calculation is
typically done to determine the standby current
of a device, and under circumstances where all of
the outputs are tri-stated or in input mode. So this
term is zero.
– Global formula for static consumption:
– P_SB = P_LC + P_LIO
Dynamic Power Consumption for UG Series
ULCs
There are four main factors to consider:
– Static power dissipation is negligible compared to
dynamic and can be ignored.
– Dc power dissipation in I/O buffers due to resistive
loads:
– P₁ (mW) = V_OL * Σ_n (D_Ln * I_OLn) + ( V_DD – V_OH)
* Σ_n (D_Hn * I_OHn)
– where: Σ_n is a summation over all of the outputs
and I/Os.
– I_OLn and I_OHn are the appropriate values for
driver n
– D_Ln = percentage of time n is being driven to V_OL
– D_Hn = percentage of time n is being driven to
V_OH
– It is difficult to obtain an exact value for this
factor, since it is determined primarily by
external system parameters. However, in
practice this can be simplified to one of two cases
where the device is either driving CMOS loads or
driving TTL loads. CMOS loads can be
5–6
approximated as purely capacitive loads,
allowing this term to be treated as zero. TTL
loads source significant current in the low state,
but not the high state, allowing the second
summation to be ignored. If a 50% duty cycle is
assumed for dynamic outputs driving TTL loads,
this can be approximated as:
– P₁ (mW) = V_OL * (Σ_n * I_OLn/2 + Σ_m * I_OLm) (TTL
loads)
– where n are dynamic outputs and m are static low
outputs.
– Dynamic power dissipation for the internal gates:
– P₂ (mW) = V_DD * I_DDOP * Σ_g (N_f * f_g)/1000
– where: N_f = number of gates toggling at
frequency f_g
– f_g = clock frequency of internal logic in MHz
– Note: If the actual toggle rates are not known, a
rule of thumb is to assume that the average used
gate is toggling at one half of the input clock
frequency.
– Dynamic power dissipation in the outputs:
– P₃ (mW) = V_DD2 * Σ_n f_n * (C_OUT + C_n)/1000
– where: f_n = clocking frequency in MHz of output
n
– C_n = output load capacitance in pF of output n
– C_OUT = output capacitance from DC
Characteristics
– Global formula for dynamic consumption:
– P = P₁ + P₂ + P₃
Example:
Static calculation
– A 100-pin ULC with 3000 used gates, 10 inputs,
20 I/Os in input mode, 40 outputs all tri-stated.
No pull-ups or pull-downs. Half of the pins are at
V_DD, half at V_SS. Input clock is not toggling. For
this example only the current calculation is
desired, so the V_DD term in the equations is
dropped.
– P_LC = 1 * 3000 = 3 mA
– P_LIO = ((10 + 20) * 5 + 40 * 5)/2 = 105 mA
– P_SB = 3 + 105 = 108 mA
Dynamic Calculation
– We take a 16-bit resettable ripple counter which
is approximately 100 gates, operating at a clock
frequency of 33 MHz, which gives an average
clock frequency of 33 MHz/16 for each bit and
each output. There are no static outputs on this
device. Operation is at 5 V, and 6-mA outputs are
used and loaded at 25 pF. The output buffers are
driving CMOS loads.
Rev. B – 25 May. 98