UG01 Datasheet, PDF (4/7 Pages) ATMEL Corporation – 0.6um ULC Series

UG Series
Internal Timing Characteristics
These timing parameters for selected macro cells are
provided for information only. Only pin-to-pin timing
characteristics are guaranteed for ULCs, and the actual
specification is determined by the original FPGA or
PLD data sheet plus any specific parameters that are
agreed to separately by Atmel Wireless &
Microcontrollers.
Conditions: V_DD = 5 V, Typical Process, Statistical Wire Length. All delays measured at V_IN/V_OUT = 2.5 V.
Macro Type
Parameter
Symbol
Min
Max^a
Max^b
Units
2-Input NAND
NAND2
0.39
0.56
4-Input NAND
Inverter
NAND4
Propagation Time
INV
t_PD
Inverting Tri-State Buffer
TRISTAN
Enable Time
t_EN
Setup Time
t_SU
Hold Time
t_H
Resetable Latch
Pulse Width
t_PW
LATCHR
Propagation Time
t_DQ
Enable Time
t_EN
Reset Time
t_RN
Setup Time
t_SU
Hold Time
t_H
D Flip-Flop with Reset
FDFFR
Pulse Width
t_PW
Clock Delay Time
t_CQ
Reset Time
t_RN
TTL Compatible Input
Buffer
BUFINTTL
t_PLH
t_PHL
TTL Compatible I/O Buffer
Input Mode
BIOT12
t_PLH
t_PHL
Propagation Time
t_PLH
Output Buffer
BOUT6
t_PHL
t_PLH
t_PLH
TTL Compatible I/O Buffer
BIOT12
t_PZH
Enable Time
t_PZL
t_PLH
Propagation Time
t_PHL
Tri-State Output Buffer
B3STA12
t_PZH
Enable Time
t_PZL
0.68
0.88
0.41
0.68
ns
0.74
0.99
0.69
0.97
0.60
0.00
0.97
1.25
1.22
1.49
0.87
1.10
0.40
0.00
0.60
0.95
1.22
0.81
0.94
0.80
0.95
0.68
0.74
ns
0.80
0.95
0.68
0.74
2.97
8.18
1.96
4.23
2.49
6.42
1.74
3.47
3.27
7.17
1.60
3.30
2.49
6.42
1.74
3.47
3.27
7.17
1.60
3.30
Notes
a. Fan-outs are three internal loads for NAND2 and NAND4, four loads for all other internal macros and input buffers. Loading of B_OUT6 is
20 pF, BIOT12 and B3STA12 are 30 pF.
b. Fan-outs are six internal loads for NAND2, seven loads for NAND4, nine loads for all other internal macros and eight for the input buffer.
Loading of B_OUT6 is 80 pF, BIOT12 and B3STA12 are 120 pF.
5–4
Rev. B – 25 May. 98