UG01 Datasheet, PDF (2/7 Pages) ATMEL Corporation – 0.6um ULC Series

UG Series
Product Outline
Part Number
UG01
UG04
UG09
UG14
UG20
UG33
UG42
UG52
UG70
UG90
UG120
UG140
Architecture
Full programmables Pads
30
48
72
88
104
130
146
162
188
212
244
264
The basic element of the UG family is called a cell. One
cell can typically implement between two to three FPGA
gates. Cells are located contiguously through out the
core of the device, with routing resources provided in
two or three metal layers above the cells. Some cell
blockage does occur due to routing, and utilization will
be significantly greater with three metal routing than
two. The sizes listed in the Product Outline are
estimated usable amounts using three metal layers. I/O
cells are provided at each pad, and may be configured as
inputs, outputs, I/Os, V_DD or V_SS as required to match
any FPGA or PLD pinout. Special function cells and
pins are located in the corners which typically are
unused.
In order to improve noise immunity within the device,
separate V_DD and V_SS busses are provided for the
internal cells and the I/O cells.
I/O Options
Inputs
Each input can be programmed as TTL, CMOS, or
Schmitt Trigger, with or without a pull up or pull down
resistor.
Fast Output Buffer
Fast output buffers are able to source or sink 3 to 12 mA
according to the chosen option. 24mA achievable, using
2 pads.
Equivalent FPGA Gates
Maximum Drive
3300
7500
15800
24300
34800
46000
58600
63700
85800
108500
145100
156800
N/A
310
790
1210
1740
2880
3660
4550
6130
7750
10360
12250
Slew Rate Controlled Output Buffer
In this mode, the p- and n-output transistor commands
are delayed, so that they are never set “ON”
simultaneously, resulting in a low switching current and
low noise. These buffer are dedicated to very high load
drive.
3.3V Compatibility
The UG series of ULCs is fully capable of supporting
high-performance operation at 3.3V or 5.0V. The
performance specifications of any given ULC design
however, must be explicitly specified as 3.3V, 5.0V or
both.
Power Supply and Noise Protection
In order to improve the noise immunity of the UG series,
several mechanisms have been implemented inside the
UG devices. Two kinds of protection have been added:
one to limit the I/O buffer switching noise and the other
to protect the I/O buffers against the switching noise
coming from the core.
I/O buffers switching protection
Three features are implemented to limit the noise
generated by the switching current: The power supplies
of the input and output buffer are separated. The rise and
fall times of the output buffers can be controlled. The
number of buffers that are connected on the same power
supply line is limited.
5–2
Rev. B – 25 May. 98