UG01 Datasheet, PDF (3/7 Pages) ATMEL Corporation – 0.6um ULC Series

UG Series
Core switching current protection
This noise disturbance is caused by a large number of
gates switching simultaneously. To allow this without
impacting the functionality of the circuit, three new
features have been added: Some decoupling capacitors
are integrated directly on the silicon to reduce the power
supply drop. A power supply network has been
implemented in the matrix. This solution lessens the
parasitic elements such as inductance and resistance and
constitutes an artificial V_DD and V_SS plane. One mesh
of the network supplies approximately 150 cells. A
low-pass filter has been added between the core and the
inputs of the output buffers. This limits the transmission
of the noise coming from the ground or the V_DD supply
of the core via the output buffers.
Absolute Maximum Ratings
Supply Voltage (V_DD) . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7.0 V
Input Voltage (V_IN) . . . . . . . . . . . . . . . . . . . –0.5 V to V_DD + 7.0 V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . –65 to 150_C
Recommended Operating Range
V_DD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V "5% or 3.3 V "5%
Operating Temperature
Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 70_C
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40 to 85_C
Military . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55 to 125_C
DC Characteristics
Parameter
Symbol
Base Part
T_A = Commercial
Min
Typ
Max Unit
Output Voltage
Input Voltage
V_OH
I_OH = 24, 12, 6, 3 depending on buffer
2.4
V_OL
I_OL = –24, –12, –6, –3 depending on buffer
V_IH
2.0
V_IL
0.4
V
0.8
V_IN = V_SS
–5
–1
Input Leakage Current
I_IX
V_IN = V_DD
V_IN = V_SS, with pull-up
1
5
–100
–40
µA
V_IN = V_DD, with pull-down
40
100
Output Leakage Current
I_OZ
V_OUT = V_SS or V_DD
–5
"1
5
Output Short Circuit Current
I_OS
V_OUT = V_DD
V_OUT = V_SS
90
160
mA
–130
–60
Standby Current
Operating Current
I_CCSB
I_DDOP
V_DD = 5.25 V, V_IN = V_SS
0.4
1
nA/Gate
0.3
0.4 _µA/Gate/
MHz
Input Capacitance
Output Capacitance
C_IN
C_OUT
V_DD = 5.0 V, V_IN = 2.0 V
V_OUT = 2.0 V
2.5
pF
2
Notes:
a. I_OH = 24, 12, 6,3. Selection determined by FPGA or PLD data sheet requirements.
Rev. B – 25 May. 98
5–3