SAM7SE256_14 Datasheet, PDF (535/682 Pages) ATMEL Corporation – Internal High-speed Flash

SAM7SE512/256/32
37. Pulse WIdth Modulation Controller (PWM)
37.1 Overview
The PWM macrocell controls several channels independently. Each channel controls one
square output waveform. Characteristics of the output waveform such as period, duty-cycle and
polarity are configurable through the user interface. Each channel selects and uses one of the
clocks provided by the clock generator. The clock generator provides several clocks resulting
from the division of the PWM macrocell master clock.
All PWM macrocell accesses are made through APB mapped registers.
Channels can be synchronized, to generate non overlapped waveforms. All channels integrate a
double buffering system in order to prevent an unexpected output waveform while modifying the
period or the duty-cycle.
37.2 Block Diagram
Figure 37-1. Pulse Width Modulation Controller Block Diagram
PWM
Controller
PWMx
Channel
Period
Update
Clock
Selector
Duty Cycle
Counter
Comparator
PWMx
PWMx
PIO
PWM0
Channel
Clock
Selector
Period
Update
Duty Cycle
Counter
Comparator
PMC
MCK
Clock Generator
APB Interface
Interrupt Generator
APB
PWM0
PWM0
AIC
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