SAM7SE256_14 Datasheet, PDF (365/682 Pages) ATMEL Corporation – Internal High-speed Flash

SAM7SE512/256/32
Note:
In the case where the arbitration is lost and TWI is addressed, TWI will not acknowledge even if it
is programmed in Slave mode as soon as ARBLST is set to 1. Then, the Master must repeat
SADR.
Figure 32-20. Programmer Sends Data While the Bus is Busy
TWCK
TWD
TWI DATA transfer
STOP sent by the master
START sent by the TWI
DATA sent by a master
Bus is busy
Transfer is kept
Bus is free
DATA sent by the TWI
A transfer is programmed
(DADR + W + START + Write THR)
Figure 32-21. Arbitration Cases
TWCK
TWD
Bus is considered as free
Transfer is initiated
TWCK
Data from a Master
Data from TWI
TWD
S 1 0 0 11
P
S 101
Arbitration is lost
TWI stops sending data
S 1 0 0 _{1 1} Data from the master P
Arbitration is lost
S 101
The master stops sending data
S 1 0 01 ₁
S 1 0 0 1 1 Data from the TWI
ARBLST
Bus is busy
Bus is free
TWI DATA transfer
Transfer is kept
A transfer is programmed
(DADR + W + START + Write THR)
Transfer is stopped
Transfer is programmed again
(DADR + W + START + Write THR)
Bus is considered as free
Transfer is initiated
The flowchart shown in Figure 32-22 on page 366 gives an example of read and write operations
in Multi-master mode.
6222H–ATARM–25-Jan-12
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