SAM7SE256_14 Datasheet, PDF (486/682 Pages) ATMEL Corporation – Internal High-speed Flash

35.8.5 SSC Transmit Clock Mode Register
Name:
SSC_TCMR
Access:
Read/Write
31
30
29
28
27
PERIOD
23
22
21
20
19
STTDLY
15
14
13
12
11
–
–
–
–
7
6
5
4
3
CKG
CKI
CKO
• CKS: Transmit Clock Selection
CKS
Selected Transmit Clock
0x0
Divided Clock
0x1
RK Clock signal
0x2
TK Pin
0x3
Reserved
26
25
24
18
17
16
10
9
8
START
2
1
0
CKS
• CKO: Transmit Clock Output Mode Selection
CKO
Transmit Clock Output Mode
0x0
None
0x1
Continuous Transmit Clock
0x2
Transmit Clock only during data transfers
0x3-0x7
Reserved
TK pin
Input-only
Output
Output
• CKI: Transmit Clock Inversion
0: The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock falling edge. The Frame sync signal
input is sampled on Transmit clock rising edge.
1: The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock rising edge. The Frame sync signal
input is sampled on Transmit clock falling edge.
CKI affects only the Transmit Clock and not the output clock signal.
486 SAM7SE512/256/32
6222H–ATARM–25-Jan-12