SAM7SE256_14 Datasheet, PDF (102/682 Pages) ATMEL Corporation – Internal High-speed Flash

Figure 19-1. Embedded Flash Memory Mapping
Start Address
Flash Memory
Lock Region 0
Lock Region 1
Lock Bit 0
Lock Bit 1
Page 0
Page (m-1)
Lock Region (n-1)
32-bit wide
Lock Bit n-1 ^{Page ( (n-1)*m )}
Page (n*m-1)
19.2.2
Read Operations
An optimized controller manages embedded Flash reads. A system of 2 x 32-bit buffers is added
in order to start access at following address during the second read, thus increasing perfor-
mance when the processor is running in Thumb mode (16-bit instruction set). See Figure 19-2,
Figure 19-3 and Figure 19-4.
This optimization concerns only Code Fetch and not Data.
The read operations can be performed with or without wait state. Up to 3 wait states can be pro-
grammed in the field FWS (Flash Wait State) in the Flash Mode Register MC_FMR (see “MC
Flash Mode Register” on page 111). Defining FWS to be 0 enables the single-cycle access of
the embedded Flash.
The Flash memory is accessible through 8-, 16- and 32-bit reads.
As the Flash block size is smaller than the address space reserved for the internal memory area,
the embedded Flash wraps around the address space and appears to be repeated within it.
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