SAM9G10_14 Datasheet, PDF (486/750 Pages) ATMEL Corporation – Additional Embedded Memories

Figure 33-4. SSC Functional Block Diagram
MCK Clock
Divider
APB
User
Interface
Transmitter
Clock Output
Controller
TK
TK Input
Transmit Clock ^{TX clock}
Frame Sync
TF
Controller
Controller
RX clock
TF
Start
RF _Selector
Transmit Shift Register
TD
Transmit Holding
Register
Transmit Sync
Holding Register
Load Shift
Receiver
Clock Output
Controller
RK
RK Input
Receive Clock ^{RX Clock}
Controller
Frame Sync
Controller
RF
TX Clock
RF
Start
TF _Selector
Receive Shift Register
RD
Interrupt Control
Receive Holding
Register
Load Shift
Receive Sync
Holding Register
NVIC
33.6.1
Clock Management
The transmitter clock can be generated by:
• an external clock received on the TK I/O pad
• the receiver clock
• the internal clock divider
The receiver clock can be generated by:
• an external clock received on the RK I/O pad
• the transmitter clock
• the internal clock divider
Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the
receiver block can generate an external clock on the RK I/O pad.
This allows the SSC to support many Master and Slave Mode data transfers.
488 SAM9G10
6462B–ATARM–6-Sep-11