SAM7S128_14 Datasheet, PDF (45/775 Pages) ATMEL Corporation – ARM-based Flash MCU

Table 11-2.
Mnemonic
AND
EOR
MUL
SMULL
SMLAL
MSR
B
BX
LDR
LDRSH
LDRSB
LDRH
LDRB
LDRBT
LDRT
LDM
SWP
MCR
LDC
ARM Instruction Mnemonic List
Operation
Logical AND
Logical Exclusive OR
Multiply
Sign Long Multiply
Signed Long Multiply Accumulate
Move to Status Register
Branch
Branch and Exchange
Load Word
Load Signed Halfword
Load Signed Byte
Load Half Word
Load Byte
Load Register Byte with Translation
Load Register with Translation
Load Multiple
Swap Word
Move To Coprocessor
Load To Coprocessor
Mnemonic
TEQ
BIC
ORR
MLA
UMULL
UMLAL
MRS
BL
SWI
STR
STRH
STRB
STRBT
STRT
STM
SWPB
MRC
STC
Operation
Test Equivalence
Bit Clear
Logical (inclusive) OR
Multiply Accumulate
Unsigned Long Multiply
Unsigned Long Multiply Accumulate
Move From Status Register
Branch and Link
Software Interrupt
Store Word
Store Half Word
Store Byte
Store Register Byte with Translation
Store Register with Translation
Store Multiple
Swap Byte
Move From Coprocessor
Store From Coprocessor
11.2.6 Thumb Instruction Set Overview
The Thumb instruction set is a re-encoded subset of the ARM instruction set.
The Thumb instruction set is divided into:
• Branch instructions
• Data processing instructions
• Load and Store instructions
• Load and Store Multiple instructions
• Exception-generating instruction
In Thumb mode, eight general-purpose registers, R0 to R7, are available that are the same physical registers as
R0 to R7 when executing ARM instructions. Some Thumb instructions also access to the Program Counter (ARM
Register 15), the Link Register (ARM Register 14) and the Stack Pointer (ARM Register 13). Further instructions
allow limited access to the ARM registers 8 to 15.
Table 11-3 gives the Thumb instruction mnemonic list.
Table 11-3.
Mnemonic
MOV
ADD
SUB
Thumb Instruction Mnemonic List
Operation
Mnemonic
Move
MVN
Add
ADC
Subtract
SBC
Operation
Move Not
Add with Carry
Subtract with Carry
SAM7S Series [DATASHEET] 45
6175M–ATARM–26-Oct-12