SAM7S128_14 Datasheet, PDF (341/775 Pages) ATMEL Corporation – ARM-based Flash MCU

30.9.5.4 Clock Synchronization
In both read and write modes, it may happen that TWI_THR/TWI_RHR buffer is not filled /emptied before the emis-
sion/reception of a new character. In this case, to avoid sending/receiving undesired data, a clock stretching
mechanism is implemented.
Clock Synchronization in Read Mode
The clock is tied low if the shift register is empty and if a STOP or REPEATED START condition was not detected.
It is tied low until the shift register is loaded.
Figure 30-27 on page 341 describes the clock synchronization in Read mode.
Figure 30-27. Clock Synchronization in Read Mode
TWI_THR
DATA0 1
DATA1
DATA2
S SADR R A DATA0 ^{A DATA1}
A
XXXXXXX
DATA2 NA S
2
TWCK
SCLWS
TXRDY
SVACC
SVREAD
TXCOMP
Write THR
CLOCK is tied low by the TWI
as long as THR is empty
As soon as a START is detected
TWI_THR is transmitted to the shift register
Ack or Nack from the master
1 ^{The data is memorized in TWI_THR until a new value is written}
2 The clock is stretched after the ACK, the state of TWD is undefined during clock stretching
Notes:
1. TXRDY is reset when data has been written in the TWI_TH to the shift register and set when this data has been acknowl-
edged or non acknowledged.
2. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from
SADR.
3. SCLWS is automatically set when the clock synchronization mechanism is started.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
341