SAM9G25_14 Datasheet, PDF (447/1167 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded Microprocessor

Read accesses to the SDRAM are burst oriented and the burst length is programmed to 8. It determines the maximum
number of column locations that can be accessed for a given read command. When the read command is issued, 8
columns are selected. All accesses for that burst take place within these eight columns, meaning that the burst wraps
within these 8 columns if the boundary is reached. These 8 columns are selected by addr[13:3]; addr[2:0] is used to
select the starting location within the block.
In the case of incrementing burst (INCR/INCR4/INCR8/INCR16), the addresses can cross the 16-byte boundary of the
SDRAM device. For example, when a transfer (INCR4) starts at address 0x0C, the next access is 0x10, but since the
burst length is programmed to 8, the next access is 0x00. Since the boundary is reached, the burst wraps. The
DDRSDRC takes into account this feature of the SDRAM device. In the case of DDR-SDRAM devices, transfers start at
address 0x04/0x08/0x0C. In the case of SDR-SDRAM devices, transfers start at address 0x14/0x18/0x1C. Two read
commands are issued to avoid wrapping when the boundary is reached. The last read command may generate
additional reading (1 read cmd = 4 DDR words or 1 read cmd = 8 SDR words).
To avoid additional reading, it is possible to use the burst stop command to truncate the read burst and to decrease
power consumption.
Figure 30-11.Single Read Access, Row Close, Latency = 2,Low-power DDR1-SDRAM Device
SDCLK
A[12:0]
COMMAND NOP PRCHG NOP
Row a Col a
ACT
NOP
READ BST
NOP
BA[1:0] ₀
DQS[1]
DQS[0]
DM[1:0] 3
D[15:0]
Da Db
Trp
Trcd
Latency = 2
SAM9G25 [DATASHEET]
Atmel-11032E-ATARM-SAMG25-Datasheet_13-Oct-14
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