SAM9G25_14 Datasheet, PDF (205/1167 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded Microprocessor

22.13.11 PMC Master Clock Register
Name:
PMC_MCKR
Address: 0xFFFFFC30
Access:
Read-write
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
–
–
–
PLLADIV2
–
–
9
8
MDIV
7
6
5
4
3
2
1
0
–
PRES
–
–
CSS
• CSS: Master/Processor Clock Source Selection
Value
Name
0
SLOW_CLK
1
MAIN_CLK
2
PLLA_CLK
3
UPLL_CLK
Description
Slow Clock is selected
Main Clock is selected
PLLACK/PLLADIV2 is selected
UPLL Clock is selected
• PRES: Master/Processor Clock Prescaler
Value
Name
0
CLOCK
1
CLOCK_DIV2
2
CLOCK_DIV4
3
CLOCK_DIV8
4
CLOCK_DIV16
5
CLOCK_DIV32
6
CLOCK_DIV64
7
CLOCK_DIV3
Description
Selected clock
Selected clock divided by 2
Selected clock divided by 4
Selected clock divided by 8
Selected clock divided by 16
Selected clock divided by 32
Selected clock divided by 64
Selected clock divided by 3
• MDIV: Master Clock Division
Value
Name
0
EQ_PCK
1
PCK_DIV2
2
PCK_DIV4
3
PCK_DIV3
Description
Master Clock is Prescaler Output Clock divided by 1.
Warning: DDRCK is not available.
Master Clock is Prescaler Output Clock divided by 2.
DDRCK is equal to MCK.
Master Clock is Prescaler Output Clock divided by 4.
DDRCK is equal to MCK.
Master Clock is Prescaler Output Clock divided by 3.
DDRCK is equal to MCK.
SAM9G25 [DATASHEET]
Atmel-11032E-ATARM-SAMG25-Datasheet_13-Oct-14
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