ATMEGA128RFA1_11 Datasheet, PDF (402/560 Pages) ATMEL Corporation – 8-bit Microcontroller with Low Power 2.4GHz Transceiver for ZigBee and IEEE 802.15.4

will lose the arbitration. Losing masters will switch to not addressed Slave mode or
wait until the bus is free and transmit a new START condition, depending on
application software action.
• Two or more masters are accessing different slaves. In this case, arbitration will
occur in the SLA bits. Masters trying to output a one on SDA while another Master
outputs a zero will lose the arbitration. Masters losing arbitration in SLA will switch to
Slave mode to check if they are being addressed by the winning Master. If
addressed, they will switch to SR or ST mode, depending on the value of the
READ/WRITE bit. If they are not being addressed, they will switch to not addressed
Slave mode or wait until the bus is free and transmit a new START condition,
depending on application software action.
This is summarized in Figure 25-21 below. Possible status values are given in circles.
Figure 25-21. Possible Status Codes Caused by Arbitration
START
SLA
Data
STOP
Arbitration lost in SLA
Arbitration lost in Data
Own
No
Address / General Call
received
Yes
Write
Direction
Read
38
TWI bus will be released and not addressed slave mode will be entered
A START condition will be transmitted when the bus becomes free
68/78
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
Last data byte will be transmitted and NOT ACK should be received
B0 ^{Data byte will be transmitted and ACK should be received}
25.9 Register Description
25.9.1 TWBR – TWI Bit Rate Register
Bit
7
6
5
4
3
2
1
0
NA ($B8)
TWBR7:0
Read/Write RW RW RW RW RW RW RW RW
Initial Value 0
0
0
0
0
0
0
0
TWBR
The SCL period is controlled by settings in the TWI Bit Rate Register (TWBR) and the
Prescaler bits in the TWI Status Register (TWSR). Slave operation does not depend on
Bit Rate or Prescaler settings, but the CPU clock frequency in the Slave must be at
least 16 times higher than the SCL frequency.
• Bit 7:0 – TWBR7:0 - TWI Bit Rate Register Value
The TWBR register selects the division factor for the bit rate generator. The bit rate
generator is a frequency divider which generates the SCL clock frequency in the Master
modes. See section "Bit Rate Generator Unit" for calculating bit rates.
402 _{ATmega128RFA1}
8266C-MCU Wireless-08/11