ATMEGA128RFA1_11 Datasheet, PDF (329/560 Pages) ATMEL Corporation – 8-bit Microcontroller with Low Power 2.4GHz Transceiver for ZigBee and IEEE 802.15.4

ATmega128RFA1
The Output Compare Register B contains an 8-bit value that is continuously compared
with the counter value (TCNT2). A match can be used to generate an Output Compare
interrupt, or to generate a waveform output on the OC2B pin.
• Bit 7:0 – OCR2B7:0 - Output Compare Register
21.11.8 ASSR – Asynchronous Status Register
Bit
7
6
5
4
3
2
1
0
NA ($B6) EXCLKAMR EXCLK AS2 TCN2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB ASSR
Read/Write
RW
RW RW R
R
R
R
R
Initial
0
0
0
0
0
0
0
0
The register ASSR controls the asynchronous clocks for Timer/Counter2 and enables
the asynchronous 32kHz clock for the symbol counter. Three bits
(AS2,EXCLK,EXCLKAMR) are used to control the clocks. Note, to prevent clock spikes
on asynchronous clock wires, every access to ASSR should change only one of the
three bits.
• Bit 7 – EXCLKAMR - Enable External Clock Input for AMR
The bit EXCLKAMR extends the available clock sources for Timer/Counter2. If this bit is
written to one, and asynchronous clock is selected (bit AS2 set), AMR functionality is
enabled and Timer/Counter2 is clocked by pin AMR.
• Bit 6 – EXCLK - Enable External Clock Input
When EXCLK is written to one, and asynchronous clock is selected, the external clock
input buffer is enabled and an external clock can be input on Timer Oscillator 1
(TOSC1) pin instead of a 32 kHz crystal. Writing to EXCLK should be done before
asynchronous operation is selected. Note that the crystal Oscillator will only run when
this bit is zero.
• Bit 5 – AS2 - Timer/Counter2 Asynchronous Mode
When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O.
When AS2 is written to one, Timer/Counter2 is clocked from a crystal Oscillator
connected to the Timer Oscillator 1 (TOSC1) pin. When the value of AS2 is changed,
the contents of TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B might be corrupted.
• Bit 4 – TCN2UB - Timer/Counter2 Update Busy
When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes
set. When TCNT2 has been updated from the temporary storage register, this bit is
cleared by hardware. A logical zero in this bit indicates that TCNT2 is ready to be
updated with a new value.
• Bit 3 – OCR2AUB - Timer/Counter2 Output Compare Register A Update Busy
When Timer/Counter2 operates asynchronously and OCR2A is written, this bit
becomes set. When OCR2A has been updated from the temporary storage register,
this bit is cleared by hardware. A logical zero in this bit indicates that OCR2A is ready to
be updated with a new value.
• Bit 2 – OCR2BUB - Timer/Counter2 Output Compare Register B Update Busy
When Timer/Counter2 operates asynchronously and OCR2B is written, this bit
becomes set. When OCR2B has been updated from the temporary storage register,
8266C-MCU Wireless-08/11
329