ATXMEGA128B1 Datasheet, PDF (38/138 Pages) ATMEL Corporation – 8/16-bit Atmel XMEGA B1 Microcontroller

21. USB – Universal Serial Bus Interface
21.1
Features
• One USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface
• Integrated on-chip USB transceiver, no external components needed
• 16 endpoint addresses with full endpoint flexibility for up to 31 endpoints
– One input endpoint per endpoint address
– One output endpoint per endpoint address
• Endpoint address transfer type selectable to
– Control transfers
– Interrupt transfers
– Bulk transfers
– Isochronous transfers
• Configurable data payload size per endpoint, up to 1023 bytes
• Endpoint configuration and data buffers located in internal SRAM
– Configurable location for endpoint configuration data
– Configurable location for each endpoint's data buffer
• Built-in direct memory access (DMA) to internal SRAM for:
– Endpoint configurations
– Reading and writing endpoint data
• Ping-pong operation for higher throughput and double buffered operation
– Input and output endpoint data buffers used in a single direction
– CPU/DMA controller can update data buffer during transfer
• Multipacket transfer for reduced interrupt load and software intervention
– Data payload exceeding maximum packet size is transferred in one continuous transfer
– No interrupts or software interaction on packet transaction level
• Transaction complete FIFO for workflow management when using multiple endpoints
– Tracks all completed transactions in a first-come, first-served work queue
• Clock selection independent of system clock source and selection
• Minimum 1.5MHz CPU clock required for low speed USB operation
• Minimum 12MHz CPU clock required for full speed operation
• Connection to event system
• On chip debug possibilities during USB transactions
21.2
Overview
The USB module is a USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface.
The USB supports 16 endpoint addresses. All endpoint addresses have one input and one output endpoint, for a total of
31 configurable endpoints and one control endpoint. Each endpoint address is fully configurable and can be configured
for any of the four transfer types: control, interrupt, bulk, or isochronous. The data payload size is also selectable, and it
supports data payloads up to 1023 bytes.
No dedicated memory is allocated for or included in the USB module. Internal SRAM is used to keep the configuration for
each endpoint address and the data buffer for each endpoint. The memory locations used for endpoint configurations
and data buffers are fully configurable. The amount of memory allocated is fully dynamic, according to the number of
endpoints in use and the configuration of these. The USB module has built-in direct memory access (DMA), and will
read/write data from/to the SRAM when a USB transaction takes place.
To maximize throughput, an endpoint address can be configured for ping-pong operation. When done, the input and
output endpoints are both used in the same direction. The CPU or DMA controller can then read/write one data buffer
while the USB module writes/reads the others, and vice versa. This gives double buffered communication.
XMEGA B1 [DATASHEET] 38
8330C–AVR–07/2012