ATXMEGA128B1 Datasheet, PDF (26/138 Pages) ATMEL Corporation – 8/16-bit Atmel XMEGA B1 Microcontroller

14. Interrupts and Programmable Multilevel Interrupt Controller
14.1
Features
• Short and predictable interrupt response time
• Separate interrupt configuration and vector address for each interrupt
• Programmable multilevel interrupt controller
– Interrupt prioritizing according to level and vector address
– Three selectable interrupt levels for all interrupts: low, medium and high
– Selectable, round-robin priority scheme within low-level interrupts
– Non-maskable interrupts for critical functions
• Interrupt vectors optionally placed in the application section or the boot loader section
14.2
Overview
Interrupts signal a change of state in peripherals, and this can be used to alter program execution. Peripherals can have
one or more interrupts, and all are individually enabled and configured. When an interrupt is enabled and configured, it
will generate an interrupt request when the interrupt condition is present. The programmable multilevel interrupt
controller (PMIC) controls the handling and prioritizing of interrupt requests. When an interrupt request is acknowledged
by the PMIC, the program counter is set to point to the interrupt vector, and the interrupt handler can be executed.
All peripherals can select between three different priority levels for their interrupts: low, medium, and high. Interrupts are
prioritized according to their level and their interrupt vector address. Medium-level interrupts will interrupt low-level
interrupt handlers. High-level interrupts will interrupt both medium- and low-level interrupt handlers. Within each level, the
interrupt priority is decided from the interrupt vector address, where the lowest interrupt vector address has the highest
interrupt priority. Low-level interrupts have an optional round-robin scheduling scheme to ensure that all interrupts are
serviced within a certain amount of time.
Non-maskable interrupts (NMI) are also supported, and can be used for system critical functions.
14.3
Interrupt vectors
The interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for specific interrupts in
each peripheral. The base addresses for the XMEGA B1 devices are shown in Table 14-1. Offset addresses for each
interrupt available in the peripheral are described for each peripheral in the XMEGA B manual. For peripherals or
modules that have only one interrupt, the interrupt vector is shown in Table 14-1. The program address is the word
address.
Table 14-1. Reset and Interrupt Vectors.
Program Address
(Base Address)
0x000
0x002
0x004
0x008
0x00C
0x014
0x018
0x01C
Source
RESET
OSCF_INT_vect
PORTC_INT_base
PORTR_INT_base
DMA_INT_base
RTC_INT_base
TWIC_INT_base
TCC0_INT_base
Interrupt Description
Crystal Oscillator Failure Interrupt vector (NMI)
Port C Interrupt base
Port R Interrupt base
DMA Controller Interrupt base
Real Time Counter Interrupt base
Two-Wire Interface on Port C Interrupt base
Timer/Counter 0 on port C Interrupt base
XMEGA B1 [DATASHEET] 26
8330C–AVR–07/2012