ATA6614Q_14 Datasheet, PDF (297/311 Pages) ATMEL Corporation – 32K Flash Microcontroller with LIN Transceiver, 5V Regulator and Watchdog

5.30 Register Summary (Continued)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
(0x8F)
Reserved
–
–
–
–
–
–
–
–
(0x8E)
Reserved
–
–
–
–
–
–
–
–
(0x8D) Reserved
–
–
–
–
–
–
–
–
(0x8C) Reserved
–
–
–
–
–
–
–
–
(0x8B)
OCR1BH
Timer/Counter1 - Output compare register B high byte
134
(0x8A)
OCR1BL
Timer/Counter1 - Output compare register B low byte
134
(0x89)
OCR1AH
Timer/Counter1 - Output compare register A high byte
134
(0x88)
OCR1AL
Timer/Counter1 - Output compare register A low byte
134
(0x87)
ICR1H
Timer/Counter1 - Input capture register high byte
135
(0x86)
ICR1L
Timer/Counter1 - Input capture register low byte
135
(0x85)
TCNT1H
Timer/Counter1 - Counter register high byte
134
(0x84)
TCNT1L
Timer/Counter1 - Counter register low byte
134
(0x83)
Reserved
–
–
–
–
–
–
–
–
(0x82)
TCCR1C FOC1A FOC1B
–
–
–
–
–
–
134
(0x81)
TCCR1B ICNC1
ICES1
–
WGM13 WGM12
CS12
CS11
CS10
133
(0x80)
TCCR1A COM1A1 COM1A0 COM1B1 COM1B0
–
–
WGM11 WGM10
131
(0x7F)
DIDR1
–
–
–
–
–
–
AIN1D
AIN0D
225
(0x7E)
DIDR0
–
–
ADC5D
ADC4D ADC3D ADC2D ADC1D
ADC0D
241
(0x7D) Reserved
–
–
–
–
–
–
–
–
(0x7C)
ADMUX REFS1 REFS0 ADLAR
–
MUX3
MUX2
MUX1
MUX0
237
(0x7B)
ADCSRB
–
ACME
–
–
–
ADTS2 ADTS1
ADTS0
241
(0x7A)
ADCSRA ADEN
ADSC
ADATE
ADIF
ADIE
ADPS2 ADPS1
ADPS0
239
(0x79)
ADCH
ADC data register high byte
240
(0x78)
ADCL
ADC data register low byte
240
(0x77)
Reserved
–
–
–
–
–
–
–
–
(0x76)
Reserved
–
–
–
–
–
–
–
–
(0x75)
Reserved
–
–
–
–
–
–
–
–
(0x74)
Reserved
–
–
–
–
–
–
–
–
(0x73)
Reserved
–
–
–
–
–
–
–
–
(0x72)
Reserved
–
–
–
–
–
–
–
–
(0x71)
Reserved
–
–
–
–
–
–
–
–
(0x70)
TIMSK2
–
–
–
–
–
OCIE2B OCIE2A
TOIE2
154
(0x6F)
TIMSK1
–
–
ICIE1
–
–
OCIE1B OCIE1A
TOIE1
135
(0x6E)
TIMSK0
–
–
–
–
–
OCIE0B OCIE0A
TOIE0
111
(0x6D)
PCMSK2 PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16
81
(0x6C)
PCMSK1
–
PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8
81
(0x6B)
PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1
PCINT0
81
(0x6A)
Reserved
–
–
–
–
–
–
–
–
Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory
addresses should never be written.
2. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVR^®s, the CBI and
SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status
flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega328P is a
complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for
the IN and OUT instructions. For the extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and
LD/LDS/LDD instructions can be used.
ATA6614Q [DATASHEET] 297
9240H–AUTO–10/14