ATA6614Q_14 Datasheet, PDF (100/311 Pages) ATMEL Corporation – 32K Flash Microcontroller with LIN Transceiver, 5V Regulator and Watchdog

Signal description (internal signals):
count
Increment or decrement TCNT0 by 1.
direction
Select between increment and decrement.
clear
Clear TCNT0 (set all bits to zero).
clk_Tn
top
Timer/Counter clock, referred to as clk_T0 in the following.
Signalize that TCNT0 has reached maximum value.
bottom
Signalize that TCNT0 has reached minimum value (zero).
Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk_T0).
clk_T0 can be generated from an external or internal clock source, selected by the clock select bits (CS02:0). When no clock
source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of
whether clk_T0 is present or not. A CPU write overrides (has priority over) all counter clear or count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/Counter control
register (TCCR0A) and the WGM02 bit located in the Timer/Counter control register B (TCCR0B). There are close
connections between how the counter behaves (counts) and how waveforms are generated on the output compare outputs
OC0A and OC0B. For more details about advanced counting sequences and waveform generation, see Section 5.14.7
“Modes of Operation” on page 102.
The Timer/Counter overflow flag (TOV0) is set according to the mode of operation selected by the WGM02:0 bits. TOV0 can
be used for generating a CPU interrupt.
5.14.5 Output Compare Unit
The 8-bit comparator continuously compares TCNT0 with the output compare registers (OCR0A and OCR0B). Whenever
TCNT0 equals OCR0A or OCR0B, the comparator signals a match. A match will set the output compare flag (OCF0A or
OCF0B) at the next timer clock cycle. If the corresponding interrupt is enabled, the output compare flag generates an output
compare interrupt. The output compare flag is automatically cleared when the interrupt is executed. Alternatively, the flag
can be cleared by software by writing a logical one to its I/O bit location. The waveform generator uses the match signal to
generate an output according to operating mode set by the WGM02:0 bits and compare output mode (COM0x1:0) bits. The
max and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some
modes of operation (Section 5.14.7 “Modes of Operation” on page 102).
Figure 5-29 shows a block diagram of the output compare unit.
Figure 5-29. Output Compare Unit, Block Diagram
DATA BUS
OCRnx
TCNTn
top
bottom
FOCn
= (8-bit Comparator)
OCFnx (Int. Req.)
Waveform Generator
OCnx
WGMn[1:0]
COMnX[1:0]
100 ATA6614Q [DATASHEET]
9240H–AUTO–10/14