ATA6614Q_14 Datasheet, PDF (142/311 Pages) ATMEL Corporation – 32K Flash Microcontroller with LIN Transceiver, 5V Regulator and Watchdog

The OCR2x register is double buffered when using any of the pulse width modulation (PWM) modes. For the normal and
clear timer on compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the
update of the OCR2x compare register to either top or bottom of the counting sequence. The synchronization prevents the
occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCR2x register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has
access to the OCR2x buffer register, and if double buffering is disabled the CPU will access the OCR2x directly.
5.17.5.1 Force Output Compare
In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the force
output compare (FOC2x) bit. Forcing compare match will not set the OCF2x flag or reload/clear the timer, but the OC2x pin
will be updated as if a real compare match had occurred (the COM2x1:0 bits settings define whether the OC2x pin is set,
cleared or toggled).
5.17.5.2 Compare Match Blocking by TCNT2 Write
All CPU write operations to the TCNT2 Register will block any compare match that occurs in the next timer clock cycle, even
when the timer is stopped. This feature allows OCR2x to be initialized to the same value as TCNT2 without triggering an
interrupt when the Timer/Counter clock is enabled.
5.17.5.3 Using the Output Compare Unit
Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle, there are risks
involved when changing TCNT2 when using the output compare channel, independently of whether the Timer/Counter is
running or not. If the value written to TCNT2 equals the OCR2x value, the compare match will be missed, resulting in
incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is
downcounting. The setup of the OC2x should be performed before setting the data direction register for the port pin to
output. The easiest way of setting the OC2x value is to use the force output compare (FOC2x) strobe bit in normal mode.
The OC2x register keeps its value even when changing between waveform generation modes.
Be aware that the COM2x1:0 bits are not double buffered together with the compare value. Changing the COM2x1:0 bits will
take effect immediately.
5.17.6 Compare Match Output Unit
The compare output mode (COM2x1:0) bits have two functions. The waveform generator uses the COM2x1:0 bits for
defining the output compare (OC2x) state at the next compare match. Also, the COM2x1:0 bits control the OC2x pin output
source. Figure 5-56 shows a simplified schematic of the logic affected by the COM2x1:0 bit setting. The I/O registers, I/O
bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR and PORT)
that are affected by the COM2x1:0 bits are shown. When referring to the OC2x state, the reference is for the internal OC2x
Register, not the OC2x pin.
142 ATA6614Q [DATASHEET]
9240H–AUTO–10/14