XMEGAD Datasheet, PDF (259/309 Pages) ATMEL Corporation – Interrupts and Programmable Multi-level Interrupt Controller

XMEGA D
Figure 22-1. The PDI with PDI physical and closely related modules (grey)
Program and Debug Interface (PDI)
PDIBUS Internal Interfaces
OCD
PDI_CLK
PDI_DATA
PDI Physical
(physical layer)
PDI
Controller
NVM
Memories
NVM
Controller
22.3
PDI Physical
The PDI physical layer handles the basic low-level serial communication. The physical layer
uses a bi-directional half-duplex synchronous serial receiver and transmitter (as a USART in
USRT mode). The physical layer includes start-of-frame detection, frame error detection, parity
generation, parity error detection, and collision detection.
The PDI is accessed through two pins:
• PDI_CLK: PDI clock input (Reset pin).
• PDI_DATA: PDI data input/output (Test pin).
In addition to these two pins, V_CC and GND must also be connected between the External Pro-
grammer/debugger and the device. Figure 22-2 on page 259 shows a typical connection.
Figure 22-2. PDI connection
PDI_CLK (RESET)
Vcc
Programmer/
Debugger
PDI_DATA (TEST)
Gnd
22.3.1 Enabling
The remainder of this section is only intended for third parties developing programming support
for XMEGA.
The PDI Physical must be enabled before it can be used. This is done by first forcing the
PDI_DATA line high for a period longer than the equivalent external reset minimum pulse width
8210B–AVR–04/10
259