XMEGAD Datasheet, PDF (138/309 Pages) ATMEL Corporation – Interrupts and Programmable Multi-level Interrupt Controller

XMEGA D
• Bit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
• Bit 2:0 – WGMODE[2:0]: Waveform Generation Mode
These bits select the Waveform Generation Mode, and control the counting sequence of the
Counter, the TOP value, the UPDATE condition, the Interrupt/event condition, and type of wave-
form that is generated, according to Table 12-3 on page 138.
No waveform generation is performed in normal mode of operation. For all other modes the
result from the waveform generator will only be directed to the port pins if the corresponding
CCxEN bit has been set to enable this. The port pin direction must be set as output.
Table 12-3. Timer Waveform Generation Mode
WGMODE[2:0]
Group
Configuration
Mode of
operation
000
NORMAL
Normal
001
FRQ
FRQ
010
Reserved
011
SS
Single Slope
PWM
100
Reserved
101
DS_T
Dual Slope PWM
110
DS_TB
Dual Slope PWM
111
DS_B
Dual Slope PWM
Top
PER
CCA
-
Update
TOP
TOP
-
PER BOTTOM
-
PER
PER
PER
-
BOTTOM
BOTTOM
BOTTOM
OVFIF/Event
TOP
TOP
-
BOTTOM
-
TOP
TOP and BOTTOM
BOTTOM
12.11.3 CTRLC - Control Register C
Bit
7
6
5
4
3
2
1
0
+0x02
–
–
–
–
CMPD
CMPC
CMPB
CMPA
CTRLC
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
• Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 3:0 – CMPx: Compare Output Value n
These bits allow direct access to the Waveform Generator's output compare value when the
Timer/Counter is set in “OFF” state. This is used to set or clear the WG output value when the
Timer/Counter is not running.
8210B–AVR–04/10
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