XMEGAD Datasheet, PDF (196/309 Pages) ATMEL Corporation – Interrupts and Programmable Multi-level Interrupt Controller

XMEGA D
17.6 Register Description
17.6.1 CTRL - SPI Control Register
Bit
+0x00
Read/Write
Initial Value
7
CLK2X
R/W
0
6
ENABLE
R/W
0
5
DORD
R/W
0
4
MASTER
R/W
0
3
2
MODE[1:0]
R/W
R/W
0
0
1
0
PRESCALER[1:0]
R/W
R/W
0
0
CTRL
• Bit 7 - CLK2X: SPI Clock Double
When this bit is set the SPI speed (SCK Frequency) will be doubled in Master mode (see Table
17-4 on page 197).
• Bit 6 - ENABLE: SPI Enable
Setting this bit enables the SPI modules. This bit must be set to enable any SPI operations.
• Bit 5 - DORD: Data Order
DORD decide the data order when a byte is shifted out from the Data register. When DORD is
written to one, the LSB of the data byte is transmitted first, and when DORD is written to zero,
the MSB of the data byte is transmitted first.
• Bit 4 - MASTER: Master/Slave Select
This bit selects Master mode when written to one, and Slave mode when written to zero. If SS is
configured as an input and is driven low while MASTER is set, MASTER will be cleared.
• Bit 3:2 - MODE[1:0]: SPI Mode
These bits select the transfer mode. The four combinations of SCK phase and polarity with
respect to serial data is shown in Figure 17-3 on page 196. This decide whether the first edge in
a clock cycles (leading edge) is rising or falling, and if data setup and sample is on lading or trail-
ing edge.
When the leading edge is rising the bit SCK is low when idle, and when the leading edge is fall-
ing the SCK is high when idle.
Table 17-3. SPI transfer modes
MODE[1:0]
00
01
10
11
Group Configuration
0
1
2
3
Leading Edge
Rising, Sample
Rising, Setup
Falling,Sample
Falling, Setup
Trailing Edge
Falling, Setup
Falling, Sample
Rising, Setup
Rising, Sample
• Bits 1:0 - PRESCALER[1:0]: SPI Clock Prescaler
These two bits control the SCK rate of the device configured in a Master mode. These bits have
no effect in Slave mode.
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