XMEGAD Datasheet, PDF (153/309 Pages) ATMEL Corporation – Interrupts and Programmable Multi-level Interrupt Controller

XMEGA D
14.4
Dead Time Insertion
The Dead Time Insertion (DTI) unit enables generation of “off” time where both the non-inverted
Low Side (LS) and inverted High Side (HS) of the WG output is low. This “off” time is called
dead-time, and dead-time insertion ensure that the LS and HS does not switch simultaneously.
The DTI unit consists of four equal dead time generators, one for each of the capture or com-
pare channel in Timer/Counter 0. Figure 14-3 on page 153 shows the block diagram of one dead
time generator. The dead time registers that define the number of peripheral clock cycles the
dead time is going to last, are common for all four channels. The High Side and Low Side can
have independent dead time setting and the dead time registers are double buffered.
Figure 14-3. Dead Time Generator block diagram
V
DTLSBUF
V
DTHSBUF
Dead Time Generator
DTILS
DTIHS
WG output
DQ
Edge Detect
LOAD _{Counter ("dti_cnt")}
E
=0
"dtls"
(To PORT)
"dths"
(To PORT)
As shown in Figure 14-4 on page 154, the 8-bit Dead Time Counter (dti_cnt) is decremented by
one for each peripheral clock cycle until it reaches zero. A non-zero counter value will force both
the Low Side and High Side outputs into their “off” state. When a change is detected on the WG
output, the Dead Time Counter is reloaded with the DTx register value according to the edge of
the input. Positive edge initiates a counter reload of the DTLS Register and a negative edge a
reload of DTHS Register.
8210B–AVR–04/10
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