XMEGAD Datasheet, PDF (151/309 Pages) ATMEL Corporation – Interrupts and Programmable Multi-level Interrupt Controller

XMEGA D
The Pattern Generation unit can be used to generate a synchronized bit pattern on the port it is
connected to. In addition, the waveform generator output from the Compare Channel A can be
distributed to and override all the port pins. When the Pattern Generator unit is enabled the DTI
unit is bypassed.
The Fault Protection unit is connected to the Event System, enabling any event to trigger a fault
condition that will disable the AWeX output.
14.3
Port Override
Common for all the timer/counter extensions is the port override logic. Figure 14-2 on page 152
shows a schematic diagram of the port override logic. When the dead-time enable (DTIENx) bit
is set the timer/counter extension takes control over the pin pair for the corresponding channel.
Given this condition the Output Override Enable (OOE) bits takes control over the CCxEN.
Note that timer/counter 1 (TCx1) can still be used even when DTI channels A, B, and D are
enabled.
8210B–AVR–04/10
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