AT17LV65A_06 Datasheet, PDF (2/18 Pages) ATMEL Corporation – FPGA Configuration EEPROM Memory

2. Pin Configuration
Figure 2-1. 8-lead PDIP
DATA 1
DCLK 2
(WP⁽¹⁾) RESET/OE 3
nCS 4
Figure 2-2. 20-lead PLCC
8 VCC
7 SER_EN
6 (A2) nCASC⁽⁴⁾
5 GND
DCLK 4
WP1⁽²⁾ 5
NC 6
NC 7
(WP⁽¹⁾) RESET/OE 8
18 SER_EN
17 NC
16 NC
15 NC (READY⁽²⁾)
14 NC
Figure 2-3. 32-lead TQFP
NC 1
DCLK 2
NC 3
(WP1⁽³⁾) NC 4
NC 5
NC 6
RESET/OE 7
NC 8
24 NC
23 SER_EN
22 NC
21 NC
20 READY
19 NC
18 NC
17 NC
Notes:
1. This pin is only available on AT17LV65A/128A/256A devices.
2. This pin is only available on AT17LV512A/010A/002A devices.
3. This pin is only available on AT17LV010A/002A devices.
4. The nCASC feature is not available on the AT17LV65A device.
2 AT17LV65A/128A/256A/512A/002A
2322G–CNFG–03/06