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AT17LV65A_06 Datasheet, PDF (11/18 Pages) ATMEL Corporation – FPGA Configuration EEPROM Memory
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AT17LV65A/128A/256A/512A/002A
19. AC Characteristics
VCC = 5V ± 5% Commercial; VCC = 5V ± 10% Industrial
AT17LV65A/128A/256A
AT17LV512A/010A/002A
Commercial
Industrial
Commercial
Industrial
Symbol
TOE(1)
TCE(1)
TCAC(1)
TOH
TDF(2)
TLC
THC
TSCE
Description
OE to Data Delay
CE to Data Delay
CLK to Data Delay
Data Hold from CE, OE, or CLK
CE or OE to Data Float Delay
CLK Low Time
CLK High Time
CE Setup Time to CLK (to guarantee proper
counting)
Min Max Min Max Min Max Min Max
30
35
30
35
45
45
45
45
50
55
50
50
0
0
0
0
50
50
50
50
20
20
20
20
20
20
20
20
35
40
20
25
THCE
CE Hold Time from CLK (to guarantee proper
counting)
0
0
0
0
THOE
FMAX
Notes:
OE High Time (guarantees counter is reset)
20
20
20
20
Maximum Input Clock Frequency
12.5
12.5
15
15
1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
20. AC Characteristics when Cascading
VCC = 5V ± 5% Commercial; VCC = 5V ± 10% Industrial
AT17LV65A/128A/256A
AT17LV512A/010A/002A
Commercial
Industrial
Commercial
Industrial
Symbol
TCDF(2)
TOCK(1)
TOCE(1)
TOOE(1)
FMAX
Description
CLK to Data Float Delay
CLK to CEO Delay
CE to CEO Delay
RESET/OE to CEO Delay
Maximum Input Clock Frequency
Min Max Min Max Min Max Min Max
50
50
50
50
35
40
35
40
35
35
35
35
30
35
30
30
10
10
12.5
12.5
Notes: 1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.
Units
ns
ns
ns
ns
MHz
11
2322G–CNFG–03/06
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