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AT17LV65A_06 Datasheet, PDF (10/18 Pages) ATMEL Corporation – FPGA Configuration EEPROM Memory
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17. AC Characteristics
VCC = 3.3V ± 10%
AT17LV65A/128A/256A
AT17LV512A/010A/002A
Commercial
Industrial
Commercial
Industrial
Symbol
TOE(1)
TCE(1)
TCAC(1)
TOH
TDF(2)
TLC
THC
TSCE
Description
OE to Data Delay
CE to Data Delay
CLK to Data Delay
Data Hold from CE, OE, or CLK
CE or OE to Data Float Delay
CLK Low Time
CLK High Time
CE Setup Time to CLK
(to guarantee proper counting)
Min Max Min Max Min Max Min Max
50
55
50
55
60
60
55
60
75
80
55
60
0
0
0
0
55
55
50
50
25
25
25
25
25
25
25
25
35
60
30
35
THCE
CE Hold Time from CLK
(to guarantee proper counting)
0
0
0
0
THOE
FMAX
Notes:
OE High Time (guarantees counter is reset)
25
25
25
25
Maximum Input Clock Frequency
10
10
15
10
1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
18. AC Characteristics when Cascading
VCC = 3.3V ± 10%
AT17LV65A/128A/256A
AT17LV512A/010A/002A
Commercial
Industrial
Commercial
Industrial
Symbol
TCDF(2)
TOCK(1)
TOCE(1)
TOOE(1)
FMAX
Description
CLK to Data Float Delay
CLK to CEO Delay
CE to CEO Delay
RESET/OE to CEO Delay
Maximum Input Clock Frequency
Min Max Min Max Min Max Min Max
60
60
50
50
55
60
50
55
55
60
35
40
40
45
35
35
8
8
12.5
10
Notes: 1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.
Units
ns
ns
ns
ns
MHz
10 AT17LV65A/128A/256A/512A/002A
2322G–CNFG–03/06
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