AT89SND2CMP3B_14 Datasheet, PDF (196/242 Pages) ATMEL Corporation – Stand-alone MP3 Decoder

Table 21-9. SSCON Register
SSCON (S:93h) – Synchronous Serial Control Register
7
6
5
4
3
SSCR2
SSPE
SSSTA
SSSTO
SSI
2
SSAA
1
SSCR1
0
SSCR0
Bit
Bit Number Mnemonic Description
7
SSCR2
Synchronous Serial Control Rate Bit 2
Refer to Table 21-1 for rate description.
Synchronous Serial Peripheral Enable Bit
6
SSPE Set to enable the controller.
Clear to disable the controller.
Synchronous Serial Start Flag
5
SSSTA Set to send a START condition on the bus.
Clear not to send a START condition on the bus.
Synchronous Serial Stop Flag
4
SSSTO Set to send a STOP condition on the bus.
Clear not to send a STOP condition on the bus.
Synchronous Serial Interrupt Flag
3
SSI
Set by hardware when a serial interrupt is requested.
Must be cleared by software to acknowledge interrupt.
Synchronous Serial Assert Acknowledge Flag
Set to enable slave modes. Slave modes are entered when SLA or GCA (if SSGC set) is
recognized.
Clear to disable slave modes.
Master Receiver Mode in progress
Clear to force a not acknowledge (high level on SDA).
Set to force an acknowledge (low level on SDA).
2
SSAA Master Transmitter Mode in progress
This bit has no specific effect when in master transmitter mode.
Slave Receiver Mode in progress
Clear to force a not acknowledge (high level on SDA).
Set to force an acknowledge (low level on SDA).
Slave Transmitter Mode in progress
Clear to isolate slave from the bus after last data Byte transmission.
Set to enable slave mode.
1
SSCR1
Synchronous Serial Control Rate Bit 1
Refer to Table 21-1 for rate description.
0
SSCR0
Synchronous Serial Control Rate Bit 0
Refer to Table 21-1 for rate description.
Reset Value = 0000 0000b
196 AT8xC51SND2C/MP3B
4341H–MP3–10/07