AT89SND2CMP3B_14 Datasheet, PDF (158/242 Pages) ATMEL Corporation – Stand-alone MP3 Decoder

When the AT8xC51SND2C is the only slave on the bus, it can be useful not to use SS# pin and
get it back to I/O functionality. This is achieved by setting SSDIS bit in SPCON. This bit has no
effect when CPHA is cleared (see Section "SS Management", page 159).
Figure 19-4. SPI Slave Mode Block Diagram
MISO/P4.2
MOSI/P4.1
I _{8-bit Shift Register} Q
SPDAT WR
SCK/P4.2
SS/P4.3
Control and Clock Logic
SSDIS
SPCON.5
CPHA
SPCON.2
CPOL
SPCON.3
SPDAT RD
SPIF
SPSTA.7
Note: 1. MSTR bit in SPCON is cleared to select slave mode.
19.1.3
19.1.4
Bit Rate
The bit rate can be selected from seven predefined bit rates using the SPR2, SPR1 and SPR0
control bits in SPCON according to Table 19-1. These bit rates are derived from the peripheral
clock (F_PER) issued from the Clock Controller block as detailed in Section "Oscillator", page 13.
Table 19-1. Serial Bit Rates
SPR2 SPR1
0
0
SPR0
6 MHz⁽¹⁾
8 MHz⁽¹⁾
Bit Rate (kHz) Vs F_PER
10 MHz⁽¹⁾ 12 MHz⁽²⁾ 16 MHz⁽²⁾
20 MHz⁽²⁾
0
3000
4000
5000
6000
8000
10000
F_PER Divider
2
0
0
1
1500
2000
2500
3000
4000
5000
4
0
1
0
750
1000
1250
1500
2000
2500
8
0
1
1
375
500
625
750
1000
1250
16
1
0
0
187.5
250
312.5
375
500
625
32
1
0
1
93.75
125
156.25
187.5
250
312.5
64
1
1
0
46.875 62.5
78.125
93.75
125
156.25
128
1
1
1
6000
8000
10000
12000
16000
20000
1
Notes: 1. These frequencies are achieved in X1 mode, F_PER = F_OSC ÷ 2.
2. These frequencies are achieved in X2 mode, F_PER = F_OSC.
Data Transfer
The Clock Polarity bit (CPOL in SPCON) defines the default SCK line level in idle state⁽¹⁾ while
the Clock Phase bit (CPHA in SPCON) defines the edges on which the input data are sampled
and the edges on which the output data are shifted (see Figure 19-5 and Figure 19-6). The SI
signal is output from the selected slave and the SO signal is the output from the master. The
AT8xC51SND2C captures data from the SI line while the selected slave captures data from the
SO line.
158 AT8xC51SND2C/MP3B
4341H–MP3–10/07