ATR2406_06 Datasheet, PDF (11/25 Pages) ATMEL Corporation – Low-IF 2.4-GHz ISM Transceiver

ATR2406
7.2 RX Register Setting
There are two RX settings possible. For a data rate of 1152 kBits/s, an internal clock recovery
function is implemented.
7.3 Register Setting Without Clock Recovery
Must be used for data rates below 1.152 Mbits/s.
MSB
LSB
Data bits
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
1
X
X
X
X
X
0
RC
MC
SC
Note: X values are not relevant and can be set to 0 or 1.
7.4 RX Register Setting with Internal Clock Recovery
Recommended for 1.152-Mbit/s data rate.
The output pin of the recovered clock is pin 6. The falling edge of the recovered clock signal
samples the data signal.
MSB
Data bits
D24
D23
D22
D21
D20
D19
D18 D17 D16
1
0
1
0
0
0
0
0
0
LSB
Data bits
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2 D1
D0
0
0
X
X
X
X
X
0
RC
MC
SC
Note: X values are not relevant and can be set to 0 or 1.
7.5 PLL Settings
RC, MC and SC bits control the synthesizer frequency as shown in Table 7-3, Table 7-4 on
page 12 and Table 7-5 on page 12.
Formula for calculating the frequency:
TX frequency: f_ANT = 864 kHz × (32 × S_MC + S_SC)
RX frequency: f_ANT = 864 kHz × (32 × S_MC + S_SC – 1)
Table 7-3.
PLL Settings of the Reference Counter Bit D7
RC (Reference Counter)
D7
CLK Reference
0
10.368 MHz
1
13.824 MHz
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4779L–ISM–09/06