AP89341_15 Datasheet, PDF (12/24 Pages) Aplus Intergrated Circuits – Integrated Circuits Inc

Integrated Circuits Inc. aP89341/170/085
• Power-down with RAMP-DOWN (PD2-A9H) or without RAMP-DOWN (PD1-E1H)
Fig. 12 Power-down commands timing
1. PDN1 will power-down the chip and set the COUT data to 00H immediately.
2. PDN2 will power-down the chip by Ramp-down the COUT from its current value to 00H.
3. Power-down will start after 350us (at 6KHz sampling rate).
4. The OUT1 pin (BUSY) will output logic HIGH during Ramp-down operation.
5. PDN2 (Power-down with ramp-down) will be executed correctly only if PU2 is
executed before.
• Set OUT2 pin status (STATUS-E3H)
Fig. 14 Setup the status of programmable output pin, OUT2
1. Signal output from the pin, OUT2, is defined by G[3:0], as below:
G[3:0]
000
001
010
011
OUT2
BUSYB
8KHz
4KHz
2KHz
G[3:0]
100
101
110
111
OUT2
1KHz
16Hz
1MHz
FULLB
2. If the STATUS is not executed, default value of OUT2 is the internal Reset signal.
3. BUSYB is the logical inversion of BUSY.
4. EMPTY (or FULLB) is the logical inversion of FULL.
5. Only the 1MHz clock will not be stopped by the PAUSE command.
Ver 5.0
11
Aug 23, 2010