AP89341_15 Datasheet, PDF (10/24 Pages) Aplus Intergrated Circuits – Integrated Circuits Inc

Integrated Circuits Inc. aP89341/170/085
CPU Parallel Trigger Mode (M1=0, M0=1)
In this mode, S8 to S1 serve as 8-bit addresses input for 254 Voice Groups with S8 represents the
MSB and S1 represents LSB. After Group address is set and ready, setting the SBT input pin to HIGH
will trigger the corresponding Voice Group to playback.
Trigger options defined in Fig. 4, 5, 7 and 8 are valid for this mode.
Fig. 10 CPU Parallel Trigger Mode
Note that SBT pin cannot be used as Single Button Sequential trigger in this mode. In stead, it acts as
a Strobe input to clock-in the Voice Group address set at S8 to S1 into the chip.
Voice Groups are represented in Binary address format. For example:
S[8:1] = 0000 0000 (00hex) for Voice Group #1
S[8:1] = 0000 0001 (01hex) for Voice Group #2
•••
S[8:1] = 0000 1000 (08 hex) for Voice Group #9
•••
S[8:1] = 1000 1000 (88 hex) for Voice Group #137
•••
S[8:1] = 1111 1101 (FD hex) for Voice Group #254
CPU Serial Command Mode (M1=1, M0=0)
This trigger mode is specially designed for simple CPU interface. The aP89341/170/085 is controlled
by command sent to it from the host CPU. S1 to S3 are used to input command word into the chip
while OUT1 to OUT3 as output from the chip to the host CPU for feedback response.
• S1 acts as CS (Chip Select) to initiate the command word input
• S2 acts as SCK (Serial Clock) to clock-in the command word at rising edge.
• S3 acts as DI (Data-In) to input the command bits.
• OUT1 acts as BUSY to indicate the chip is in busy state.
• OUT2 acts as POUT to output user selected information.
• OUT3 acts as FULL signal to indicate the Voice Group address buffer is full.
Command input into the chip may contains 8-bit or 16-bit data. The first 8-bit data is command bits
while the second 8-bit data (if any) is the Voice Group address data. Table 1 summarize the available
commands and their functions.
Ver 5.0
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Aug 23, 2010